IBM breaks the 1nm barrier with next-generation chip architecture

BM has unveiled what it calls the world's first sub-1 nanometer chip technology, marking a significant step toward the next era of semiconductor innovation. Developed using a new three-dimensional "nanostack" architecture, the breakthrough packs nearly 100 billion transistors onto a fingernail-sized chip—almost double the density of IBM's 2 nm technology introduced in 2021.

Rather than simply shrinking transistors further, IBM's approach stacks them vertically, opening a new path for continued performance gains as conventional scaling reaches its physical limits. According to the company, the new architecture could deliver up to 50% higher performance or reduce power consumption by as much as 70% compared with its 2 nm platform. It also improves SRAM scaling by around 40%, an important advantage for AI inference and data-intensive workloads.

The technology is expected to benefit future AI accelerators, high-performance computing, cloud infrastructure and advanced mobile processors, where higher transistor density and lower energy consumption are becoming increasingly critical.

While the sub-1 nm technology remains a research breakthrough rather than a commercial product, IBM believes it can be manufactured using existing semiconductor processes with further development. The company expects the technology to reach production within the next five years through industry partners, extending the roadmap for next-generation chip manufacturing.