Taiyo Advances Semiconductor packaging with 700-nm RDL Formation on 12-inch Wafers

Taiyo Holdings Co., Ltd. has introduced its next-generation FPIM Series semiconductor-packaging material, reporting the successful formation of a three-layer redistribution layer with 700-nm lines and vias on 12-inch wafers.

Developed through joint research with imec, the technology represents progress toward submicron redistribution layer design rules for advanced semiconductor packaging. Taiyo presented the latest results at the IEEE Electronics System-Integration Technology Conference 2026 in Helsinki, Finland.

Redistribution layers, commonly known as RDLs, provide the electrical connections that reroute signals between semiconductor dies and external terminals. They have become increasingly important as chipmakers adopt advanced packaging technologies to combine processors, memory and other components within compact, high-performance systems.

Demand for finer RDL features is growing as artificial intelligence, high-performance computing and other data-intensive applications require greater interconnect density, faster signal transmission and improved power efficiency.

FPIM Material Supports Dual-Damascene Processing

Taiyo’s FPIM Series is a negative-tone, i-line photosensitive insulating material designed for fine-pitch RDL fabrication using a dual-damascene process.

Most RDL structures are currently produced through a semi-additive process. In this approach, manufacturers typically form an insulating layer, create vias and then build copper interconnects through several deposition, lithography and plating stages.

Dual-damascene processing forms the trenches and vias within an insulating material before filling them with metal. The approach can simplify the creation of multilayer interconnect structures and may become increasingly important as RDL dimensions move toward 1.6 µm and below.

However, producing increasingly narrow lines and vias places demanding requirements on photosensitive insulating materials. These materials must provide high resolution, dimensional stability, electrical insulation and compatibility with other manufacturing steps, including chemical mechanical polishing.

Taiyo said its FPIM material demonstrated the resolution and electrical characteristics required for three-layer RDL fabrication at a 700-nm critical dimension. The metal 1 layer also showed favorable leakage-current and resistance performance.

The research further confirmed the material’s compatibility with chemical mechanical polishing, a process used to remove excess material and create a flat surface before subsequent interconnect layers are formed.

Joint Research Moves Below Previous 1.6-µm Milestone

Taiyo and imec began their joint research program in October 2022. In November 2025, the companies reported the formation of a three-layer RDL structure with a critical dimension of 1.6 µm on 12-inch wafers.

The latest demonstration reduces that dimension to 700 nm for both the interconnect lines and vias, marking a significant step toward submicron RDL fabrication.

Taiyo described the result as the first successful formation of a three-layer RDL at this dimension using its FPIM Series material on 12-inch wafers.

Shrinking RDL dimensions can allow more electrical connections to be placed within a smaller area. This could help semiconductor manufacturers integrate chiplets and other components more densely while supporting the high-bandwidth communication required by advanced processors.

Targeting 500-nm Features and Below

Taiyo is now targeting RDL formation with critical dimensions of 500 nm or less. The company also plans to continue evaluating the long-term electrical performance and reliability of the material.

Reliability testing will be important before the technology can progress from research to high-volume production. Advanced packaging materials must maintain their properties through manufacturing processes and withstand thermal and mechanical stresses during the operating life of a device.

Taiyo began shipping small-volume samples of the FPIM Series for research and development applications in 2025. These samples allow semiconductor manufacturers and research institutions to evaluate the material within emerging packaging processes.

The development comes as the semiconductor industry increasingly turns to advanced packaging to overcome the technical and economic limits of conventional transistor scaling. Chiplet architectures, heterogeneous integration and high-bandwidth memory require increasingly sophisticated interconnect structures between components.

Materials capable of supporting finer RDL features could therefore play a critical role in the production of next-generation AI accelerators, high-performance computing devices and other advanced semiconductors.

Taiyo’s 700-nm demonstration suggests that photosensitive insulating materials and dual-damascene processing may provide a pathway toward denser multilayer interconnects on large-diameter wafers. Further testing and process development will determine how quickly the technology can move toward commercial-scale semiconductor packaging.